Học FPGA

Tutorial - What is a Tri-State Buffer Why are tristate buffers needed in half-duplex communication How to infer tri-state buffers in Verilog and VHDL Tri-State buffers are able to be in one of three states: Logic 0, Logic 1, and Z (high impedance). Their use allows for multiple drivers to share a common line. This makes them particularly useful in half-duplex communications. Let's first discuss the difference between half-duplex and full-duplex communications. Half Duplex vs. Full Duplex The common analogy to is to think of a two-way radio. The speaker is only able to transmit when he holds the button on the radio. When the speaker is transmitting the listener is unable to transmit. The speaker and listener must agree whose turn it is to talk. This is why you often hear, "over" in the movies, it means the speaker is done talking. This is an example of a half-duplex system. A full duplex system is one in which the speaker and listener can both speak and listen at the same ...